A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, is capable of storing two bits of data in a double-bit arrangement. That is, one bit can be stored using a first charge storing region on a first side of the memory device and a second bit can be stored using a second charge storing region on second side of the memory device.
As shown in FIG. 1, in a conventional charge trapping dielectric memory device 10, the charge storing regions 36, 38 are part of a non-conductive charge trapping layer 28 that is disposed between a relatively thick (e.g., about 100 angstroms) bottom (or tunnel) dielectric layer 26 and a relatively thick (e.g., 100 angstroms) top dielectric layer 30. These dielectric layers 26, 28, 30 can be formed over a P-type conductivity silicon substrate 12 having a series of bitlines BL1, BL2, disposed therein. A series of conductive wordlines WL made from polycrystalline silicon is formed over the dielectric layers 26, 28, 30 for serving as a gate electrode 32 for each memory device 10. The core memory devices 10 can be addressed by applying appropriate voltages to the wordline WL and/or bitlines BL1, BL2.
During programming and reading of the core memory devices 10, the bitlines BL1, BL2 can function as a source 14 (i.e., a source of electrons or holes) and a drain 16 with an active channel region defined therebetween. Programming of such a memory device can be accomplished, for example, by hot electron injection. Hot electron injection involved applying appropriate voltage potentials to each of the gate electrode 32, the source 14, and the drain 16 of the memory device 10 for a specified duration until the charge trapping layer 28 accumulates charge.
Where possible, it is desirable to downscale memory devices, while still maintaining desirable qualities, such as adequate data retention, and optimizing performance. However, memory device downscaling can result in a number of performance degrading effects. For example, in memory devices with an active channel region having a relatively short length, a memory device can experience a number of undesirable electrical characteristics referred to as short channel effects (SCE). SCE generally occur when the gate electrode does not have adequate control over the active channel region, and can include threshold voltage (VT) roll off, off current (Ioff) roll-up and drain induced barrier lowering (DIBL). As the physical dimensions of the device decrease, SCE can be become more severe.
Where possible, it is also desirable to reduce the amount of power used to operate (e.g., program, read and/or erase) memory devices.
Accordingly, there is a need in the art for improved memory devices, such as charge trapping dielectric flash memory devices, that optimize scale, power consumption and performance.